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TIMER0_DTCTRL. If more bits are still set in DTFS when the automatic startup functionality has cleared
the debugger bit, the DTI module does not exit the fault state. The fault state is only exited when all the
bits in TIMER0_DTFS have been cleared.
19.3.3.4 Configuration Lock
To prevent software errors from making changes to the DTI configuration, a configuration lock is
available. Writing any value but 0xCE80 to LOCKKEY in TIMER0_DTLOCK results in TIMER0_DTFC,
TIMER0_DTCTRL, TIMER0_DTTIME and TIMER0_ROUTE being locked for writing. To unlock the
registers, write 0xCE80 to LOCKKEY inTIMER0_DTLOCK. The value of TIMER0_DTLOCK is 1 when
the lock is active, and 0 when the registers are unlocked.
19.3.4 Debug Mode
When the CPU is halted in debug mode, the Timer can be configured to either continue to run or to be
frozen. This is configured in DBGHALT in TIMERn_CTRL.
19.3.5 Interrupts, DMA and PRS Output
The Timer has 5 output events:
? Counter Underflow
? Counter Overflow
? Compare match or input capture (one per Compare/Capture channel)
Each of the events has its own interrupt flag. Also, there is one interrupt flag for each Compare/Capture
channel which is set on buffer overflow in capture mode. Buffer overflow happens when a new capture
pushes an old unread capture out of the TIMERn_CCx_CCV/TIMERn_CCx_CCVB register pair.
If the interrupt flags are set and the corresponding interrupt enable bits in TIMERn_IEN) are set high,
the Timer will send out an interrupt request. Each of the events will also lead to a one HFPERCLK TIMERn
cycle high pulse on individual PRS outputs.
Each of the events will also set a DMA request when they occur. The different DMA requests are cleared
when certain acknowledge conditions are met, see Table 19.3 (p. 259) . If DMACLRACT is set in
TIMERn_CTRL, the DMA request is cleared when the triggered DMA channel is active, without having
to access any timer registers.
Table 19.3. TIMER Events
Underflow/Overflow
CC 0
CC 1
CC 2
Event
Acknowledge
Read or write to TIMERn_CNT or TIMERn_TOPB
Read or write to TIMERn_CC0_CCV or
TIMERn_CC0_CCVB
Read or write to TIMERn_CC1_CCV or
TIMERn_CC1_CCVB
Read or write to TIMERn_CC2_CCV or
TIMERn_CC2_CCVB
19.3.6 GPIO Input/Output
The TIMn_CCx inputs/outputs and TIM0_CDTIx outputs are accessible as alternate functions through
GPIO. Each pin connection can be enabled/disabled separately by setting the corresponding CCxPEN
or CDTIxPEN bits in TIMERn_ROUTE. The LOCATION bits in the same register can be used to move
all enabled pins to alternate pins.
2011-04-12 - d0001_Rev1.10
259
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